1. Field of the Invention
The present invention relates to high speed digital circuits, and in particular, to high speed time-division multiplexor circuits.
2. Description of the Related Art
Modern data networks in which multiple computers are interconnected for sharing instructions and data, e.g., local area networks ("LANs"), typically operate over a serial data medium. The computers themselves, however, typically process their instructions or data internally in parallel formats. Therefore, to interface to the data network, each computer must use an M:1 multiplexor to transfer data or instructions into the network, where M is the number of parallel bits of instructions or data which must be time-division multiplexed into a serial bit stream.
As shown in FIG. 1, an M:1 multiplexor has M inputs D.sub.0 -D.sub.M-1, a clock input CLK for clocking the M parallel data inputs D.sub.0 -D.sub.M-1 into the multiplexor, a serial data output Q, and a trigger output T. The clock input signal CLK must have a frequency equal to the bit rate of the serial output signal Q. The trigger output T has a frequency equal to that of the clock input signal (i.e., the bit rate of the serial output Q) divided by the number M of parallel data input bits. Thus, the clock input signal CLK must have a frequency equal to M times the bit rate of the parallel data inputs D.sub.0 -D.sub.M-1.
FIG. 2 illustrates, for the case of M=4 bits, a simple type of time-division multiplexor based upon an M-bit shift register. The input data bits D.sub.0 -D.sub.3 are loaded in parallel on every fourth clock pulse, with the most significant bit D.sub.3 being loaded into a D-type flip-flop, and the less significant bits D.sub.0 -D.sub.2 being loaded into 2:1 interleavers, e.g., multiplexors. On the other three clock pulses the data is shifted serially to the output Q. The clock signal CLK, used to clock the D-type flip-flops in the shift register, is also frequency-divided to produce the clock, or select S, signals for the 2:1 interleavers and the trigger output T.
With a shift register based, time-division multiplexor as shown in FIG. 2, it will be appreciated that the shift register section requires the following: ##EQU1##
It will be further appreciated that the bit rate limitation for the load pulse generation section, i.e., the frequency divider section, of the multiplexor of FIG. 2 can be shown to be similar. Thus, the maximum bit rate for the multiplexor architecture of FIG. 2 is determined in accordance with the following: ##EQU2##
In practice, however, the shift register based, time-division multiplexor of FIG. 2 cannot achieve this theoretical maximum speed due to the effects of signal delay variations among the various signal paths for the input and output signals. Furthermore, the multiplexor of FIG. 2 must be operated with a clock signal frequency equal to the outgoing bit rate. This can be a problem when this type of multiplexor is used to interface with a very high speed data network medium, such as an optical fiber. Full advantage of the extremely high bit rate capabilities of an optical fiber cannot be realized by simply clocking a solid state electronic multiplexor at a higher rate. In other words, the electronics simply cannot reliably keep pace with the elevated bit rates possible with optical fibers.
In an attempt to increase the architecturally limited maximum bit rate of the multiplexor of FIG. 2, and to overcome the requirement of using a clock signal having a frequency equal to the outgoing bit rate, the interleaved, time-division multiplexor of FIG. 3 was developed. (As in FIG. 2, the illustrated multiplexor in FIG. 3 is for the case of M=4 bits.) The four parallel input bits D.sub.0 -D.sub.3 are loaded simultaneously into D-type flip-flops, the outputs of which are interleaved with two 2:1 multiplexors. The outputs of the two multiplexors are then, in turn, multiplexed with another 2:1 multiplexor to produce the serial output Q. The flip-flops and first two multiplexors are clocked with various phases of the frequency-divided clock signal. The output multiplexor is clocked directly by the input clock signal, but at a delayed point in time in accordance with a time delay introduced by a delay line.
The input clock signal for the multiplexor of FIG. 3 has a frequency which is half that of the clock signal for the multiplexor of FIG. 2. It is further frequency-divided with multiple phases by coupling two D-type flip-flops together as a divide-by-two frequency divider circuit.
For the multiplexor of FIG. 3, it will be appreciated that the input data flip-flops, in conjunction with the clock divider flip-flops, requires the following: ##EQU3##
Within the interleaving output stages, each 2:1 multiplexor requires only that data be valid at its output within one bit period T.sub.bit. This in theory requires the following: EQU T.sub.bit &gt;T.sub.D1,2.fwdarw.Q
Therefore: ##EQU4##
Hence, the interleaved time-division multiplexor of FIG. 3 appears to be faster than the shift register based, time-division multiplexor of FIG. 2 by a factor of three. However, the interleaved multiplexor of FIG. 3 with single phase input latches and a clock delay line has practical limitations. First, fabricating an optimum delay line for the clock signal, required for ensuring clocking of the final 2:1 multiplexor at the proper time so as to achieve maximum bit rate, is very difficult due to normal semiconductor fabrication process variations. Second, the use of single stage, single phase input latches requires that each input data bit be latched through its input latch stage and through its first interleaver stage within one bit period T.sub.bit. In other words, this requires the following: EQU T.sub.bit &gt;T.sub.CLK.fwdarw.Q +T.sub.D1,2.fwdarw.Q
Thus, since the overall maximum bit rate cannot exceed the maximum bit rate of the slowest portion of the circuit, the maximum bit rate for the interleaved multiplexor of FIG. 3 is the following: ##EQU5##
Hence, the interleaved time-division multiplexor of FIG. 3 is no faster in theory than the shift register based, time-division multiplexor of FIG. 2.
Thus, it would be desirable to have an M:1 time-division multiplexor with an architecture providing a higher maximum bit rate while still requiring a clock signal having a frequency lower than the outgoing serial bit rate. It would be further desirable to have such a multiplexor with the foregoing characteristics without requiring a delay line for phase compensating the clock signal for the final interleaving stage. This is particularly desirable for M.gtoreq.8 bits since multiple matched delay lines for phase compensating multiple clock signals having different frequencies are then required.